In the fabrication of semiconductor microelectronic circuits, chemical vapor deposition processes are employed to fill deep narrow openings or high aspect ratio (HAR) openings, such as isolation trenches and deep contacts. The aspect ratio (the height to diameter ratio) may range from 5:1 to greater than 10:1. Several processes have been employed for this purpose, including sub-atmospheric chemical vapor deposition (SACAVD), plasma enhanced chemical vapor deposition (PECVD) and high density plasma chemical vapor deposition (HDPCVD).
The SACVD process, when used to deposit a silicon dioxide film, typically uses a metal-organic silicide gas such as tri-ethyl ortho-silicate (TEOS) gas and ozone in a vacuum chamber containing the silicon wafer. The deposition reaction is a thermal reaction carried out at an elevated wafer temperature (e.g., about 500° C.), in which the heat dissociates free oxygen from the ozone gas and silicon from the TEOS molecules, and promotes surface mobility of deposited atoms on the coating. The deposition reaction is conformal, forming a coating of a nearly uniform thickness on both horizontal and vertical surfaces on the semiconductor wafer. Although the reaction is carried out in a vacuum, the chamber pressure is high (e.g., a few hundred Torr) relative to other CVD processes. This relatively high pressure is required to compensate for the slow deposition rate of the SACVD process. Although the wafer temperature is elevated during the deposition to about 500° C., the deposited coating must be annealed at about 700°-900° C. The SACVD process is unsuitable for use on devices having feature sizes 65 nanometers or smaller, and particularly for filling HAR openings in such small devices. First, the deposition rate is slow and the wafer throughput is low. Secondly, this process requires a wafer anneal step, which adds to the production cost of each wafer. Also, the high process temperature and time, and the high (900° C.) anneal temperature required in the SACVD process causes small features (such as doped sources and drains) to diffuse over a significant distance for some applications. Such thermal induced diffusion may cause the source-to-drain channel length to shrink under a permissible threshold below which device failure can occur. Finally, the SACVD process is so conformal that the deposition rate on vertical side walls of HAR openings is as great as the deposition rate on horizontal surfaces (and perhaps greater than on the horizontal bottom surface of a HAR opening). This makes its impossible to completely fill the bottom of a 65 nanometer HAR opening before the top of the opening is pinched off due to accumulation along the vertical side wall. Such accumulation is favored near the top of the side wall of an HAR opening, and will therefore completely block the opening before the bottom of the opening is completely filled. This leaves a void inside the opening, which is unacceptable. A further disadvantage of the SACVD process is that it is relatively slow, requiring that the semiconductor wafer be maintained at the elevated (500° C.) temperature during deposition for a relatively long time, thereby limiting productivity and increasing the thermal diffusion of 65 nanometer features on the wafer.
The PECVD process is carried out at a lower pressure (e.g., 5-15 Torr) than the SACVD process, but attains a higher deposition rate by utilizing a low density plasma to dissociate TEOS and oxygen. In a parallel plate reactor, the low density plasma is generated by applying an RF potential on the order of about a few hundred volts across the plates. The ion to neutral ratio in the low density plasma is quite low (about 10−8 to 10−4), and therefore the process is dominated by neutrals. The plasma enhancement of the deposition favors deposition on horizontal surfaces more than vertical surfaces, although the step coverage ratio (vertical wall deposition rate to horizontal wall deposition rate) can be as high as 50%. As a result, when the PECVD process is used for 65 nanometer devices, deposition near the top of the side walls of HAR openings pinches off the openings before they can be filled from the bottom, leaving voids in the openings. This problem can be alleviated somewhat by sputtering of the top edges of the HAR openings (to reduce the deposition rate near the tops of the openings). The problem is that the sputtering efficiency of the low density plasma employed in the PECVD process is poor. This is due to the relatively low plasma ion density (obtained at the low voltage of the plasma source) and because the chamber pressure (5-15 Torr) is too high for efficient sputtering. As a result, sputtering of the top edges of the HAR openings does not always prevent the pinch-off problem. Therefore, the PECVD process is not suitable for filling HAR openings in small (e.g., 65 nanometer) devices.
The HDPCVD process employs a high density plasma at low pressure to promote sputtering of the top corners. To achieve a high ion density, the chamber pressure is maintained at a very low level (e.g., 1-18 mT) using about 10 kW of source power (e.g., for a 300 mm diameter wafer) and a very high bias power (about 2 to 10 kW). The resulting ion density is about 1×1017 to 3×1017 m−3 for a molecular process gas (such as silane) and about 5×1017 to 1018 m−3 for an atomic process gas (such as Argon). The ion to neutral ratio in the high density plasma is higher than in PECVD (about 10−3 to 10−2). The high bias power produces higher ion energies but does not increase the sheath voltage (or the peak ion energies) beyond about 1000 volts, due to the higher conductivity of the plasma. Under such conditions, the sputtering efficiency is quite good, and is sufficient to reduce the deposition rate near the top edges of HAR openings to prevent pinch-off, at least for large geometry devices. For this purpose, the process gas may include silane and oxygen (for silicon dioxide deposition) and Argon (for sputtering).
As device features are reduced in size, redeposition of sputtered material from one corner occurs at the opposing corner, eventually pinching off the gap. Helium substituted in place of Argon in the HDPDVD process allows filling gaps of higher aspect ratio. At even higher aspect ratio, Hydrogen is substituted for the Helium, producing better gap fill results. The hydrogen performs some sputtering but also performs some chemical etching at the top edges of HAR openings, and provides the best possible sputtering efficiency. This allows the HDPCVD process to be used to fill HAR openings in very small devices approaching 65 nanometers. However, at 65 nanometers, the sputtered material on one side of each HAR opening top edge tends to land on the opposite side, so that there is very little or no net reduction of the accumulation of deposited species at the HAR opening top edge. As a result, at 65 nanometers, the HDPCVD process fails because of pinch-off of HAR openings before they can be completely filled from the bottom. Even at low pressure and high plasma density (ion to neutral ratio about 10−3 to 10−2) the process is still dominated by neutrals, leading to eventual pinch-off before small high-aspect-ratio gaps can be filled.
In summary, the advance in semiconductor technology toward 65 nanometer feature sizes is frustrated because of a lack of a reliable chemical vapor deposition process capable of completely filling HAR openings. There is therefore a great need for a chemical vapor deposition process capable of doing so.